1. Field of the Invention
The present invention relates to a data transfer circuit, a solid-state imaging device represented by a CMOS image sensor and a camera system.
2. Description of the Related Art
In recent years, as a solid-state imaging device used as an image sensor to replace a CCD, a CMOS image sensor has been attracting attention.
This is because special processes are required in fabricating a CCD pixel and, in addition, a plurality of power-supply voltages are needed in order to operate the CCD pixel. On top of that, in the case of the CCD, it is necessary to combine a plurality or peripheral chips and operate the chips. The CMOS image sensor is thus used as a sensor for solving a variety of problems each raised in a system based on CCD pixels as a problem making the system complicated.
The CMOS image sensor can be fabricated by adoption of a manufacturing process identical with the process for fabricating an ordinary CMOS integrated circuit. In addition, the CMOS image sensor can be driven by making use of a single power supply. On top of that, an analog circuit and a logic circuit, which are created by adopting the CMOS process, can be mixed with each other on the same chip as the CMOS image sensor. Thus, the CMOS image sensor offers a plurality of big merits including a decreased number of peripheral ICs.
The data outputting circuit of a CCD is usually a 1-channel data outputting circuit employing an FD (floating diffusion) amplifier having an FD layer. In the case of a CMOS image sensor, on the other hand, each pixel generally employs an FD amplifier. A row of a pixel array is selected and pieces of information are read out at the same time from pixels on the selected row in the row direction to generate an output of the CMOS image sensor. Thus, the output of the CMOS image sensor is generally an output parallel to the pixel rows of the pixel array.
This is because, with an FD amplifier embedded in a pixel, it is difficult to provide a sufficient driving power. It is thus necessary to reduce the data rate and parallel processing is regarded as advantageous processing.
There have been proposed a great variety of data outputting circuits of the CMOS image sensor having an output parallel to the pixel rows of the pixel array as described above. In accordance with one of most advanced types of the data outputting circuit, each column is provided with an analog-digital conversion device for outputting a pixel signal as a digital signal. In the following description, the analog-digital conversion device is referred to as an ADC (analog digital converter).
A CMOS image sensor employing an on-a-row ADC for every pixel column is disclosed in documents such as W. Yang et al., “An Integrated 800×600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, February 1999 and Japanese Patent Laid-open No. 2005-323331.
FIG. 1 is a block diagram showing a typical configuration of a solid-state imaging device 1 (also referred to as a CMOS image sensor) employing an on-a-row ADC for each pixel column.
As shown in the figure, the solid-state imaging device 1 employs a pixel-array section 2 serving as an imaging unit, a row scan circuit 3, a column scan circuit 4, a timing control circuit 5, an ADC group 6, a digital-analog converter 7, a counter 8 and an data outputting circuit 9 including a plurality of S/A (sense amplifier) circuits. In the following description, the digital-analog converter 7 is referred to merely as a DAC.
The pixel-array section 2 is a matrix of unit pixels 2-1 each including a photo diode and an in-pixel amplifier. The timing control circuit 5 is a circuit for generating internal clock signals whereas the row scan circuit 3 is a circuit for generating row addresses and for controlling a row scan operation. The column scan circuit 4 is a circuit for generating column addresses and for controlling a column scan operation. In the solid-state imaging device 1, the row scan circuit 3, the column scan circuit 4 and the timing control circuit 5 are employed as control circuits for reading out a signal from the pixel-array section 2.
The ADC group 6 having a function to convert an analog signal into digital data of n bits forms and including an ADC block 6-3 for a plurality of column lines V0, V1 and so on. To put it in detail, the ADC group 6 employs the same plurality of comparators 6-1 each connected to one of the pixel column lines V0, V1 and so on and the same plurality of memory units 6-2 each associated with one of the comparators 6-1. Each of the comparators 6-1 compares a ramp-waveform reference voltage RAMP generated by the DAC 7 as a signal having a staircase waveform with an analog signal generated by a unit pixel 2-1 selected by one of row lines H0, H1 and so on and connected to the comparator 6-1 by one of the pixel column lines V0, V1 and so on. Each of the memory units 6-2 is used for storing the contents of the counter 8 which carries out a counting operation to measure the length of the time of the comparison carried out by the comparator 6-1. Each particular one of the comparators 6-1 and a memory unit 6-2 connected to the particular comparator 6-1 form the aforementioned on-a-row ADC is provided.
The output of the memory unit 6-2 is connected to a horizontal data transfer line 6-4 having a width of 2n bits, that is, 2n horizontal data transfer lines. The horizontal data transfer line 6-4 is also connected to an output circuit through the data outputting circuit 9 including 2n sense amplifiers for the 2n bits respectively.
Operations carried out by the solid-state imaging device 1 (also referred to as a CMOS image sensor) are explained by referring to timing charts shown in FIG. 2 and the block diagram of FIG. 1 as follows.
After a first operation to read out data from unit pixels 2-1 on a row Hx and transfer the data to the pixel column lines V0, V1 and so on becomes stable, the DAC 7 supplies a ramp-waveform reference voltage RAMP as a signal having a staircase waveform to the comparators 6-1. The comparators 6-1 each compare the ramp-waveform reference voltage RAMP with a voltage appearing on the pixel column line Vx.
While the DAC 7 is supplying the ramp-waveform reference voltage RAMP as a signal having a staircase waveform to the comparator 6-1, the counter 8 carries out a first counting operation for the first read operation. When the ramp-waveform reference voltage RAMP becomes equal to the voltage appearing on the pixel column line Vx, the output of the comparator 6-1 is inverted in order to store the contents of the counter 8 in the memory unit 6-2 as data representing the length of the time of the comparison. In the first read operation, a reset component ΔV of the unit pixel 2-1 is read out. The reset component ΔV includes a noise varying by unit pixel as an offset. In general, however, variations in reset component ΔV are small. In addition, a reset level is uniform for all the unit pixels 2-1. Thus, the output of any column line Vx is known approximately.
Thus, by adjusting the ramp-waveform reference voltage RAMP in the first read operation to read out the reset component ΔV, the time of the comparison carried out by the comparator 6-1 can be made short. In this example, the comparison is carried out as counting data of 7 bits representing up to 128 clock pulses.
The second read operation is carried out in the same way as the first one described above. In the second read operation, however, a reset component ΔV and a signal component representing an incident-light quantity are read out from the unit pixel 2-1.
To put it in detail, after the second operation to read out data from unit pixels 2-1 on a row Hx and transfer the data to the pixel column lines V0, V1 and so on becomes stable, the DAC 7 supplies the ramp-waveform reference voltage RAMP as a signal having a staircase waveform to the comparators 6-1. The comparators 6-1 each compare the ramp-waveform reference voltage RAMP with the voltage arbitrary appearing on the pixel column line Vx.
While the DAC 7 is supplying the ramp-waveform reference voltage RAMP as a signal having a staircase waveform, the counter 8 carries out a counting operation for the second read operation. When the RAMP becomes equal to the voltage appearing on the pixel column line Vx, the output of the comparator 6-1 is inverted in order to store the contents of the counter 8 in the memory unit 6-2. The length of the time of the comparison carried out by the comparator 6-1 in the second read operation is stored at a location different from the location for storing the length of the time of the comparison carried out by the comparator 6-1 in the first read operation.
At the end of the AD conversion processes described above, the column scan circuit 4 transfers an n-bit digital signal representing the length of the time of the comparison carried out by the comparator 6-1 in the first read operation and an n-bit digital signal representing the length of the time of the comparison carried out by the comparator 6-1 in the second read operation from the memory unit 6-2 to the data outputting circuit 9 by way of the horizontal data transfer line 6-4 having a width of 2n bits. In the data outputting circuit 9, a sequential subtraction circuit subtracts the n-bit digital signal representing the length of the time of the comparison carried out in the first read operation from the n-bit digital signal representing the length of the time of the comparison carried out in the second read operation and outputs the difference to an external circuit as a result of the subtraction. Then, the same operations are carried out sequentially for each row in order to generate a 2-dimensional image.